
W9816G6IH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
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11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
DQ
Q0
Q1
Q2
Q3
Q4
( b )CAS latency = 3
Command
Read
BST
DQ
Q0
Q1
Q2
Q3
Q4
(2) Write cycle
Command
Write
BST
DQ
Q0
Q1
Q2
Q3
Q4
Note:
BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
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11
(1 ) R e a d c y c le
(a ) C A S la te n c y = 2
C om m and
Read
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(b ) C A S la te n c y = 3
C om m and
Read
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(2 ) W r ite c y c le
C om m and
W rite
tW R
PRCG
DQM
DQ
Q0
Q1
Q2
Q3
Q4
Publication Release Date: Mar. 22, 2010
- 38 -
Revision A02